[VHDL]스탑워치 설계

소개글

VHDL을 이용한 스탑워치 설계입니다.

목차

☉스탑워치 VHDL 설계☉
☉시뮬레이션 결과 값☉
☉스위치☉
☉디지털 시계 VHDL 설계☉
☉시뮬레이션 결과 값☉
☉스위치☉

본문내용

☉스탑워치 VHDL 설계☉

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity stop is

PORT(
CLK : in std_logic;
SW_A : in std_logic;
SW_B : in std_logic;
SW_C : in std_logic;
SW_D : in std_logic;
SEG_DATA : out std_logic_vector(7 downto 0);
SEG_COM : buffer std_logic_vector(7 downto 0)
);
end stop;

architecture arc of stop is

signal mode : std_logic_vector(2 downto 0);
signal SW_A_Q1, SW_A_Q2 : std_logic;
signal SW_B_Q1, SW_B_Q2 : std_logic;
signal SW_C_Q1, SW_C_Q2 : std_logic;
signal SW_D_Q1, SW_D_Q2 : std_logic;
signal msec : integer range 0 to 9999;
signal seg5,seg6 : std_logic_vector(7 downto 0);
signal seg7,seg8 : std_logic_vector(7 downto 0);
signal temp : integer range 0 to 9999;
signal temp1 : integer range 0 to 9999;
signal cnt : integer range 0 to 999;
function seven (display: integer range 0 to 10)
return std_logic_vector is
variable seg_data: std_logic_vector (7 downto 0);
begin

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