연세대 전기전자 기초실험 09년도 A+ 레포트 예비 7
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- 2009.12.17
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- 2009.05
- 8페이지/ 한컴오피스
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연세대학교 전기전자 기초실험 09년도 A+ 레포트
목차
Chapter 7 Basic Logic Circuit Design
① Explain how to design logic gates with transistors.
② Design XOR gate with minimum 2 input AND, OR, NAND, NOR, NOT gates.
③ Describe the followings : TTL(Transistor Transistor Logic), ECL(Emitter Coupled Logic), MOS(Metal Oxide Semiconductor), CMOS(Complementary Metal Oxide Semiconductor)
④ Using Karnaugh map, express boolean algebra equation from T/F table.
⑤ Build boolean algebra equation of full/half subtractor.
본문내용
③ Describe the followings : TTL(Transistor Transistor Logic), ECL(Emitter Coupled Logic), MOS(Metal Oxide Semiconductor), CMOS(Complementary Metal Oxide Semiconductor)
1) TTL (Transistor Transistor Logic)
Transistor–transistor logic (TTL) is a class of digital circuits built from bipolar junction transistors (BJT) and resistors. It is called transistor–transistor logic because both the logic gating function (e.g., AND) and the amplifying function are performed by transistors (contrast this with RTL and DTL).
2) ECL (Emitter Coupled Logic)
In electronics, emitter-coupled logic, or ECL, is a logic family in which current is steered through bipolar transistors to implement logic functions. ECL is sometimes called current-mode logic[2] or current-switch emitter-follower (CSEF) logic.
Fig 9. Motorola ECL 10,000 basic gate circuit diagram The chief characteristic of ECL is that the transistors are never in the saturation region and can thus change states at very high speed. Its major disadvantage is that the circuit continuously draws current, which means it requires a lot of power.
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