반도체 공정 프로젝트

소개글

성균관대 반도체 공정 수업에서 설계과제로 나온 프로젝트입니다.
5개의 질문에 대한 답을 한것입니다.

목차

1. These days, in order to improve the device performance, some high performance devices are built on a SOI wafer structure. By referring to the literatures and internet, design a process sequence making a SOI structure (similar to the process sequence description shown in the integration chapter) and explain the details of each unit process.

2. Design a step-by-step process sequence in building the CMOSFET structure shown in the following figure. At each step, comment what kind of method.

3. After making the SALICIDE struture, PECVD- layer is
deposited on the entire wafer (See layer `a` in the figure).
Why do we need that layer?

4. As ILD and IMD layers, PSG and SOD were used, respectively.
What are PSG and SOD? Explain why these materials or
deposition techniques are needed instead of typical PECVD-

5. In making Cu metallization scheme, PECVD-grown SiC ("b" layers) is used as a etching/CMP stop layer between SOC layers instead of PECVD-grown . What will be the benefit of SiC instead of ?

본문내용

1. These days, in order to improve the device performance, some high performance devices are built on a SOI wafer structure. By referring to the literatures and internet, design a process sequence making a SOI structure (similar to the process sequence description shown in the integration chapter) and explain the details of each unit process.
2. Design a step-by-step process sequence in building the CMOSFET structure shown in the following figure. At each step, comment what kind of method.
3. After making the SALICIDE struture, PECVD-Si3N4 layer is
deposited on the entire wafer (See layer `a` in the figure).
Why do we need that layer?
4. As ILD and IMD layers, PSG and SOD were used, respectively.
What are PSG and SOD? Explain why these materials or
deposition techniques are needed instead of typical PECVD-SiO2.
5. In making Cu metallization scheme, PECVD-grown SiC ("b" layers) is used as a etching/CMP stop layer between SOC layers instead of PECVD-grown . What will be the benefit of SiC instead of ?




5. In making Cu metallization scheme, PECVD-grown SiC ("b" layers) is used as a etching/CMP stop layer between SOC layers instead of PECVD-grown . What will be the benefit of SiC instead of ?
-Consistent and fairly predictable improvement in integrated circuit design and fabrication has been observed in the last decade. One key to successful improvements is the multilevel interconnect technology, which provides the conductive paths between the devices of an integrated circuit (IC) device. The shrinking dimensions of features, presently in the sub-quater micron and smaller range, such as horizontal interconnects and vertical interconnects in very large scale integration (VLSI) and ultra large scale integration (ULSI) technology, has increased the importance of reducing the dielectric constant of the many layers and the capacitive coupling between interconnect lines. In order to further improve the speed of integrated circuit, it has become necessary to use materials having law resistivity and low (dielectric constant less than 7.0) insulators to reduce the capacitive coupling between adjacent metal lines.

참고 자료

[1] 반도체공정기술, 황호정 저, 생능출판사, 2003
[2] A Study on the Fabrication of LDD-typed nMOSFET with Shallow junction
formed by RTA of Phosphorus doped PSG Film, 류장렬, 홍봉식, 충남대학교, 1994.
[3] Ion-cut에 의한 SOI 웨이퍼 제조 및 특성조사, 우형주 외 3인, Journal of the Korean Vacuum Society Vol. 14, No. 2, 2005, pp.91~96
[4] Smart-cut 기술의 이온 주입과 웨이퍼 접합을 이용한 SOI 웨이퍼 제작 관한 연구, 김형권, 연세대학교, 2004
[5] IN SITU DEPOSITION OF LOW K SI CARBIDE BARRIER LAYER, ETCH STOP, AND ANTI-REFLECTIVE COATING FOR DAMASCENE APPLICATIONS, HUANG, Judy, APPLIED MATERIALS,INC, 2000
[6] Introduction to Microelectronic Fabrication(2/E), Richard C. Jaeger, Pearson Education