실험6.레지스터 구성

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본문내용

Chapter 1. 관련 이론(Theoretical Background)
자리이동 레지스터(Shift Register)
: 각 플립플롭의 출력이 옆에 있는 플립플롭의 입력에 차례로 연결되어 있어서 클럭펄스가 들어올 때마다 저장된 이진 정보가 한자리씩 옆으로 이동되는 레지스터
Shift resgister 의 종류
Serial-in/serial-out, Parallel-in/serial-out, Serial-in/parallel-out, Universal Parallel-in/parallel-out, Ring counter
74LS74[DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP]
The SN54/ 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.

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