쿼터스를 이용한 CPU의 ALU 설계 (모델심 추가)

소개글

CPU 만들기 위한 ALU입니다

과제 제출용이며 확실히 돌아갑니다^^

컴파일 실행환경

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압축파일 내 파일목록

ALU.asm.rpt
ALU.done
ALU.dpf
ALU.eda.rpt
ALU.fit.rpt
ALU.fit.summary
ALU.flow.rpt
ALU.map.rpt
ALU.map.summary
ALU.pin
ALU.pof
ALU.qpf
ALU.qsf
ALU.qsf.bak
ALU.sof
ALU.tan.rpt
ALU.tan.summary
ALU.v
ALU.v.bak
ALU_nativelink_simulation.rpt
db/ALU.(0).cnf.cdb
db/ALU.(0).cnf.hdb
db/ALU.(1).cnf.cdb
db/ALU.(1).cnf.hdb
db/ALU.(2).cnf.cdb
db/ALU.(2).cnf.hdb
db/ALU.(3).cnf.cdb
db/ALU.(3).cnf.hdb
db/ALU.(4).cnf.cdb
db/ALU.(4).cnf.hdb
db/ALU.(5).cnf.cdb
db/ALU.(5).cnf.hdb
db/ALU.(6).cnf.cdb
db/ALU.(6).cnf.hdb
db/ALU.amm.cdb
db/ALU.asm.qmsg
db/ALU.asm.rdb
db/ALU.cbx.xml
db/ALU.cmp.cbp
db/ALU.cmp.kpt
db/ALU.cmp.rdb
db/ALU.cmp0.ddb
db/ALU.cmp_merge.kpt
db/ALU.db_info
db/ALU.eda.qmsg
db/ALU.fit.qmsg
db/ALU.hier_info
db/ALU.hif
db/ALU.idb.cdb
db/ALU.lpc.html
db/ALU.lpc.rdb
db/ALU.lpc.txt
db/ALU.map.cbp
db/ALU.map.kpt
db/ALU.map.qmsg
db/ALU.map_bb.hdb
db/ALU.pre_map.cdb
db/ALU.pre_map.hdb
db/ALU.rpp.qmsg
db/ALU.rtlv.hdb
db/ALU.rtlv_sg.cdb
db/ALU.rtlv_sg_swap.cdb
db/ALU.sgate.rvd
db/ALU.sgate_sm.rvd
db/ALU.sgdiff.cdb
db/ALU.sgdiff.hdb
db/ALU.sld_design_entry.sci
db/ALU.sld_design_entry_dsc.sci
db/ALU.smart_action.txt
db/ALU.syn_hier_info
db/ALU.tan.qmsg
db/ALU.tis_db_list.ddb
db/logic_util_heursitic.dat
db/prev_cmp_ALU.qmsg
incremental_db/compiled_partitions/ALU.db_info
incremental_db/compiled_partitions/ALU.root_partition.cmp.cdb
incremental_db/compiled_partitions/ALU.root_partition.cmp.dfp
incremental_db/compiled_partitions/ALU.root_partition.cmp.hdb
incremental_db/compiled_partitions/ALU.root_partition.cmp.kpt
incremental_db/compiled_partitions/ALU.root_partition.cmp.logdb
incremental_db/compiled_partitions/ALU.root_partition.cmp.rcfdb
incremental_db/compiled_partitions/ALU.root_partition.cmp.re.rcfdb
incremental_db/compiled_partitions/ALU.root_partition.map.cdb
incremental_db/compiled_partitions/ALU.root_partition.map.dpi
incremental_db/compiled_partitions/ALU.root_partition.map.hdb
incremental_db/compiled_partitions/ALU.root_partition.map.kpt
incremental_db/README
place_ALU.v.bak
simulation/modelsim/ALU.sft
simulation/modelsim/ALU.vo
simulation/modelsim/ALU_modelsim.xrf
simulation/modelsim/ALU_run_msim_rtl_verilog.do
simulation/modelsim/ALU_run_msim_rtl_verilog.do.bak
simulation/modelsim/ALU_run_msim_rtl_verilog.do.bak1
simulation/modelsim/ALU_run_msim_rtl_verilog.do.bak10
simulation/modelsim/ALU_run_msim_rtl_verilog.do.bak11
simulation/modelsim/ALU_run_msim_rtl_verilog.do.bak2
simulation/modelsim/ALU_run_msim_rtl_verilog.do.bak3
simulation/modelsim/ALU_run_msim_rtl_verilog.do.bak4
simulation/modelsim/ALU_run_msim_rtl_verilog.do.bak5
simulation/modelsim/ALU_run_msim_rtl_verilog.do.bak6
simulation/modelsim/ALU_run_msim_rtl_verilog.do.bak7
simulation/modelsim/ALU_run_msim_rtl_verilog.do.bak8
simulation/modelsim/ALU_run_msim_rtl_verilog.do.bak9
simulation/modelsim/ALU_v.sdo
simulation/modelsim/modelsim.ini
simulation/modelsim/msim_transcript
simulation/modelsim/rtl_work/@a@l@u/verilog.prw
simulation/modelsim/rtl_work/@a@l@u/verilog.psm
simulation/modelsim/rtl_work/@a@l@u/_primary.dat
simulation/modelsim/rtl_work/@a@l@u/_primary.dbs
simulation/modelsim/rtl_work/@a@l@u/_primary.vhd
simulation/modelsim/rtl_work/@a@n@d_@g@a@t@e/verilog.prw
simulation/modelsim/rtl_work/@a@n@d_@g@a@t@e/verilog.psm
simulation/modelsim/rtl_work/@a@n@d_@g@a@t@e/_primary.dat
simulation/modelsim/rtl_work/@a@n@d_@g@a@t@e/_primary.dbs
simulation/modelsim/rtl_work/@a@n@d_@g@a@t@e/_primary.vhd
simulation/modelsim/rtl_work/@f@u@l@l_@a@d@d@e@r/verilog.prw
simulation/modelsim/rtl_work/@f@u@l@l_@a@d@d@e@r/verilog.psm
simulation/modelsim/rtl_work/@f@u@l@l_@a@d@d@e@r/_primary.dat
simulation/modelsim/rtl_work/@f@u@l@l_@a@d@d@e@r/_primary.dbs
simulation/modelsim/rtl_work/@f@u@l@l_@a@d@d@e@r/_primary.vhd
simulation/modelsim/rtl_work/@f@u@l@l_@a@d@d@e@r_32/verilog.prw
simulation/modelsim/rtl_work/@f@u@l@l_@a@d@d@e@r_32/verilog.psm
simulation/modelsim/rtl_work/@f@u@l@l_@a@d@d@e@r_32/_primary.dat
simulation/modelsim/rtl_work/@f@u@l@l_@a@d@d@e@r_32/_primary.dbs
simulation/modelsim/rtl_work/@f@u@l@l_@a@d@d@e@r_32/_primary.vhd
simulation/modelsim/rtl_work/@m@u@x_1/verilog.prw
simulation/modelsim/rtl_work/@m@u@x_1/verilog.psm
simulation/modelsim/rtl_work/@m@u@x_1/_primary.dat
simulation/modelsim/rtl_work/@m@u@x_1/_primary.dbs
simulation/modelsim/rtl_work/@m@u@x_1/_primary.vhd
simulation/modelsim/rtl_work/@m@u@x_2/verilog.prw
simulation/modelsim/rtl_work/@m@u@x_2/verilog.psm
simulation/modelsim/rtl_work/@m@u@x_2/_primary.dat
simulation/modelsim/rtl_work/@m@u@x_2/_primary.dbs
simulation/modelsim/rtl_work/@m@u@x_2/_primary.vhd
simulation/modelsim/rtl_work/@o@r_@g@a@t@e/verilog.prw
simulation/modelsim/rtl_work/@o@r_@g@a@t@e/verilog.psm
simulation/modelsim/rtl_work/@o@r_@g@a@t@e/_primary.dat
simulation/modelsim/rtl_work/@o@r_@g@a@t@e/_primary.dbs
simulation/modelsim/rtl_work/@o@r_@g@a@t@e/_primary.vhd
simulation/modelsim/rtl_work/tb_@a@l@u/verilog.prw
simulation/modelsim/rtl_work/tb_@a@l@u/verilog.psm
simulation/modelsim/rtl_work/tb_@a@l@u/_primary.dat
simulation/modelsim/rtl_work/tb_@a@l@u/_primary.dbs
simulation/modelsim/rtl_work/tb_@a@l@u/_primary.vhd
simulation/modelsim/rtl_work/_info
simulation/modelsim/rtl_work/_temp/
simulation/modelsim/rtl_work/_vmake
simulation/modelsim/vsim.wlf
tb_ALU.v
tb_ALU.v.bak

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