카이스트 전자공학실험2 실험1 Combinational Logic Design, Flip-Flop, and Counter 결과보고서

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카이스트 전자공학실험2 실험1 결과보고서입니다.

목차

1. Objectives
2. Problem Statement
3. Experiment Outline
4. Pre-requisite
5. Experiment
6. Examination
7. Reference
8. 고찰

본문내용

1. Objectives
- Understand the operation of combinational logic circuits
- Understand how to simplify the Boolean function using Karnaugh map
- Understand the operation of flip-flop.
- Implement simple digital logic circuits.

2. Problem Statement
1) Implement Magnitude Comparator
2) Implement BCD - to - 7 segment display code converter
3) Implement synchronous counter & asynchronous counter.
4) Display the counter value on 7 segment LED.

3. Experiment Outline
[Combinational logic]
1) Implementing combinational logic
To design a combinational logic circuit, we should understand the specification of the given problem and generate a truth table which contains all possible input values and their corresponding outputs. From this truth table, the output can be represented as a Boolean function (in the form of min-terms, or max-terms) and a combinational logic circuit can be derived directly from the Boolean function. In the logic design, it is important to reduce the number of gates and, therefore, the propagation delay of circuits, which can be achieved by applying the logic minimization to the Boolean equation. To minimize Boolean equations, Karnaugh map or Quine-McCluskey methods are widely used. For cases when the number of inputs is less than five, Karnaugh map is usually used, while, for other cases, Quine-McCluskey method is used. After logic minimization, the combinational logic circuit can be implemented by using basic logic devices like AND, OR, NOT, etc.

2) Design steps of combination logic circuits
A. Define inputs and outputs.
B. Consider the correlation between inputs and outputs and make a truth table.
C. Simplify the Boolean function of the output.
D. Implement the Boolean function using gates.

[Flip-Flop & Counter]

1) Memory Devices

R-S latch(Fig.1) has the simplest internal architecture among lots of memory devices. The output Q of R-S latch goes HIGH when input S(Set) becomes high. In addition, The output Q goes LOW when input R(Reset) becomes HIGH.

참고 자료

Contemporary Logic Design - Katz
Fundamentals of Logic Design - Roth