전기전자기초실험 Chapter 10 Flip-Flop andCounter DesignReport
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- 2011.12.18
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- 2011.10
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2011년 2학기 전기전자기초실험 보고서입니다. 전부 다 영어로 작성되어 있으며, 예비보고서의 경우 주석 충분히 달려 있습니다. 베끼지 않고 작성하여, 이 자료를 쓰셔도 Cheating의 염려가 없습니다. 코딩은 직접 작성하였으며, 전부 주석이 달려 있습니다. 코딩 동작 확인하였습니다.
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본문내용
In this waveform, OUT values increases since PL=1 and U_D=0. When PL=0, OUT gets value P of the time when PL goes to 0. When PL=1 and U_D=1, OUT values decreases.
② Explain the setup time, hold time in D Flip-Flop.
Since Logic circuit are not ideal in reality, change of signal is not applied instantly on circuits and logic circuit needs time to understand and calculate the signals. Setup time(Tsu) is the minimum time delay that inputting D signal before triggered clock signal. Hold time(Tsu) is the minimum time delay that maintaining D signal after triggered clock signal. In reality, input signal must be remained on setup time and hold time to work D flip-flop smoothly.[1]
③ Find out the application of flip-flops.
Filp-flop is the simple logic circuit that using clock signal and past output to get present output(1-bit). Since it uses feedback, it can be called memorable. Flip-flop is the basic element of the memory device, so it is applied in many devices. More complicated logic circuits use flip-flops, like register and counter, and moreover, memory cells and processing units use flip-flops. In simple logic circuits, D flip-flop used in giving delay, T flip-flop used in counting numbers, and JK flip-flop used in choosing and setting data that needs to be memorized.[2]
참고 자료
Charles H. Roth, Jr. (2006). Analysis of Clocked Sequential Circuits, Unit 13, page 376
Charles H. Roth, Jr. (2006). Latches and Flip-Flops, Unit 11, page 301-306