전기전자기초실험 Chapter 11 FSM(Finite State Machine) Design Report

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2011년 2학기 전기전자기초실험 보고서입니다. 전부 다 영어로 작성되어 있으며, 예비보고서의 경우 주석 충분히 달려 있습니다. 베끼지 않고 작성하여, 이 자료를 쓰셔도 Cheating의 염려가 없습니다. 코딩은 직접 하였으며, 전부 주석이 달려 있습니다. 코딩 동작 확인하였습니다.

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·FSM(Finite State Machine) Design
① Do some research on the circuits using Mealy machien and Moore machine.
FSM is a kind of logic circuit that has finite states. This machine has some states and it can be changed of remained by input signals. Also, output signals are made by input signals by each state differently.[1] It has two kind of state graphs which is similar to flow chart, Mealy state graph and Moore state graph. This two kind of graphs are different in getting output signals, so the expression of graphs is different. In Mealy state graph, output signals depend on current states and input signals, so each state is written in state symbol and each input and output value are written on directional arrow. In Moore state graph, output signals depend on only on current state, so each state and output value are written in state symbol and each input value is written on directional arrow.[2]

② Optimize the FSM in Figure 11-3 by designing it differently.
This FSM makes the output 1 when continuous input sequences make groups of numbers, 11 and 1111. After output 1 when input sequence is 1111, next input signal is ignored whatever that is 0 or 1. Making this FSM with effective way is code below.

참고 자료

Charles H. Roth, Jr. (2006). Derivation of State Graphs and Tables, Unit 12, page 393-397
FSM[Online]. Available: http://en.wikipedia.org/wiki/Finite_state_machine