altera quatusII DE2보드를 이용한 디지털 시계(알람, 타이머, am/pm, 시간설정)
*은*
다운로드
장바구니
소개글
저번학기 프로젝트로 만든 디지털 시계 입니다.처음부터 끝까지 제가 만든거라 제출하여도 카피 뜰 걱정없어여~
본문 내용이 수정이 안돼서 여기에 핀설정방법올려여
입력 5개 있는데
클럭은 50mhz
c/m/s_data, reset push button 1234
lcd 제어 및 데이터명은 테이블 보고 맞춰 넣으심 되고요
led 도 숫자 맞춰 넣어주시면 끝입니다
컴파일 실행환경
quartus II본문내용
device family : cyclone IIavailable device : EP2C35F672C6
pin 설정
clk, reset, c_mode, s_data, c_data : in std_logic;
clk
압축파일 내 파일목록
dclk/db/
dclk/db/dclk.(0).cnf.cdb
dclk/db/dclk.(0).cnf.hdb
dclk/db/dclk.asm.qmsg
dclk/db/dclk.asm_labs.ddb
dclk/db/dclk.cbx.xml
dclk/db/dclk.cmp.bpm
dclk/db/dclk.cmp.cdb
dclk/db/dclk.cmp.ecobp
dclk/db/dclk.cmp.hdb
dclk/db/dclk.cmp.kpt
dclk/db/dclk.cmp.logdb
dclk/db/dclk.cmp.rdb
dclk/db/dclk.cmp.tdb
dclk/db/dclk.cmp_merge.kpt
dclk/db/dclk.cmp0.ddb
dclk/db/dclk.db_info
dclk/db/dclk.eco.cdb
dclk/db/dclk.fit.qmsg
dclk/db/dclk.hier_info
dclk/db/dclk.hif
dclk/db/dclk.map.bpm
dclk/db/dclk.map.cdb
dclk/db/dclk.map.ecobp
dclk/db/dclk.map.hdb
dclk/db/dclk.map.kpt
dclk/db/dclk.map.logdb
dclk/db/dclk.map.qmsg
dclk/db/dclk.map_bb.cdb
dclk/db/dclk.map_bb.hdb
dclk/db/dclk.map_bb.hdbx
dclk/db/dclk.map_bb.logdb
dclk/db/dclk.pre_map.cdb
dclk/db/dclk.pre_map.hdb
dclk/db/dclk.psp
dclk/db/dclk.rtlv.hdb
dclk/db/dclk.rtlv_sg.cdb
dclk/db/dclk.rtlv_sg_swap.cdb
dclk/db/dclk.sgdiff.cdb
dclk/db/dclk.sgdiff.hdb
dclk/db/dclk.sld_design_entry.sci
dclk/db/dclk.sld_design_entry_dsc.sci
dclk/db/dclk.smp_dump.txt
dclk/db/dclk.syn_hier_info
dclk/db/dclk.tan.qmsg
dclk/db/dclk.tis_db_list.ddb
dclk/db/prev_cmp_dclk.asm.qmsg
dclk/db/prev_cmp_dclk.fit.qmsg
dclk/db/prev_cmp_dclk.map.qmsg
dclk/db/prev_cmp_dclk.qmsg
dclk/db/prev_cmp_dclk.tan.qmsg
dclk/dclk.asm.rpt
dclk/dclk.done
dclk/dclk.dpf
dclk/dclk.fit.rpt
dclk/dclk.fit.smsg
dclk/dclk.fit.summary
dclk/dclk.flow.rpt
dclk/dclk.map.rpt
dclk/dclk.map.summary
dclk/dclk.pin
dclk/dclk.pof
dclk/dclk.qpf
dclk/dclk.qsf
dclk/dclk.qws
dclk/dclk.sof
dclk/dclk.tan.rpt
dclk/dclk.tan.summary
dclk/dclk.vhd
dclk/dclk.vhd.bak
dclk/incremental_db/
dclk/incremental_db/compiled_partitions/
dclk/incremental_db/compiled_partitions/dclk.root_partition.cmp.atm
dclk/incremental_db/compiled_partitions/dclk.root_partition.cmp.dfp
dclk/incremental_db/compiled_partitions/dclk.root_partition.cmp.hdbx
dclk/incremental_db/compiled_partitions/dclk.root_partition.cmp.kpt
dclk/incremental_db/compiled_partitions/dclk.root_partition.cmp.logdb
dclk/incremental_db/compiled_partitions/dclk.root_partition.cmp.rcf
dclk/incremental_db/compiled_partitions/dclk.root_partition.map.atm
dclk/incremental_db/compiled_partitions/dclk.root_partition.map.dpi
dclk/incremental_db/compiled_partitions/dclk.root_partition.map.hdbx
dclk/incremental_db/compiled_partitions/dclk.root_partition.map.kpt
dclk/incremental_db/README
dclk/undo_redo.txt
dclk/db/dclk.(0).cnf.cdb
dclk/db/dclk.(0).cnf.hdb
dclk/db/dclk.asm.qmsg
dclk/db/dclk.asm_labs.ddb
dclk/db/dclk.cbx.xml
dclk/db/dclk.cmp.bpm
dclk/db/dclk.cmp.cdb
dclk/db/dclk.cmp.ecobp
dclk/db/dclk.cmp.hdb
dclk/db/dclk.cmp.kpt
dclk/db/dclk.cmp.logdb
dclk/db/dclk.cmp.rdb
dclk/db/dclk.cmp.tdb
dclk/db/dclk.cmp_merge.kpt
dclk/db/dclk.cmp0.ddb
dclk/db/dclk.db_info
dclk/db/dclk.eco.cdb
dclk/db/dclk.fit.qmsg
dclk/db/dclk.hier_info
dclk/db/dclk.hif
dclk/db/dclk.map.bpm
dclk/db/dclk.map.cdb
dclk/db/dclk.map.ecobp
dclk/db/dclk.map.hdb
dclk/db/dclk.map.kpt
dclk/db/dclk.map.logdb
dclk/db/dclk.map.qmsg
dclk/db/dclk.map_bb.cdb
dclk/db/dclk.map_bb.hdb
dclk/db/dclk.map_bb.hdbx
dclk/db/dclk.map_bb.logdb
dclk/db/dclk.pre_map.cdb
dclk/db/dclk.pre_map.hdb
dclk/db/dclk.psp
dclk/db/dclk.rtlv.hdb
dclk/db/dclk.rtlv_sg.cdb
dclk/db/dclk.rtlv_sg_swap.cdb
dclk/db/dclk.sgdiff.cdb
dclk/db/dclk.sgdiff.hdb
dclk/db/dclk.sld_design_entry.sci
dclk/db/dclk.sld_design_entry_dsc.sci
dclk/db/dclk.smp_dump.txt
dclk/db/dclk.syn_hier_info
dclk/db/dclk.tan.qmsg
dclk/db/dclk.tis_db_list.ddb
dclk/db/prev_cmp_dclk.asm.qmsg
dclk/db/prev_cmp_dclk.fit.qmsg
dclk/db/prev_cmp_dclk.map.qmsg
dclk/db/prev_cmp_dclk.qmsg
dclk/db/prev_cmp_dclk.tan.qmsg
dclk/dclk.asm.rpt
dclk/dclk.done
dclk/dclk.dpf
dclk/dclk.fit.rpt
dclk/dclk.fit.smsg
dclk/dclk.fit.summary
dclk/dclk.flow.rpt
dclk/dclk.map.rpt
dclk/dclk.map.summary
dclk/dclk.pin
dclk/dclk.pof
dclk/dclk.qpf
dclk/dclk.qsf
dclk/dclk.qws
dclk/dclk.sof
dclk/dclk.tan.rpt
dclk/dclk.tan.summary
dclk/dclk.vhd
dclk/dclk.vhd.bak
dclk/incremental_db/
dclk/incremental_db/compiled_partitions/
dclk/incremental_db/compiled_partitions/dclk.root_partition.cmp.atm
dclk/incremental_db/compiled_partitions/dclk.root_partition.cmp.dfp
dclk/incremental_db/compiled_partitions/dclk.root_partition.cmp.hdbx
dclk/incremental_db/compiled_partitions/dclk.root_partition.cmp.kpt
dclk/incremental_db/compiled_partitions/dclk.root_partition.cmp.logdb
dclk/incremental_db/compiled_partitions/dclk.root_partition.cmp.rcf
dclk/incremental_db/compiled_partitions/dclk.root_partition.map.atm
dclk/incremental_db/compiled_partitions/dclk.root_partition.map.dpi
dclk/incremental_db/compiled_partitions/dclk.root_partition.map.hdbx
dclk/incremental_db/compiled_partitions/dclk.root_partition.map.kpt
dclk/incremental_db/README
dclk/undo_redo.txt
참고 자료
없음이 자료와 함께 구매한 자료
- VHDL Stop Watch를 이용한 스톱워치 설계 7페이지
- [전기전자] 교통신호 제어기에 관한 VHDL 코딩 4페이지
- [정보통신] VHDL을 이용한 신호등 제어 5페이지
- [vhdl]신호등 제어하는 코딩 (vhdl) 5페이지
- 완벽 스탑워치 소스!!!! 0페이지