[영문 전기.전자공학 학부 졸업논문] 0.3V에서 동작하는 터널링 트랜지스터 개발

목차

ABSTRACT ii

1 Introduction 1

2 Theoretical Background 2
2.1 Tunneling Field-Effect Transistor 2
2.2 Green Transistor 3
2.3 The SOI Structure 3

3 Simulation Setup 5

4 Results and Discussions 7
4.1 Leakage Current 7
4.2 Operating Voltage (Vdd) 11
4.3 0.3V-operating Tunneling Transistor 16

5 Conclusion 18

References

본문내용

1. Introduction

The Moore’s law dictates that every two years the number of transistors per IC chip doubles. And accordingly, the IC power consumption is increasing. However, the battery capacity cannot afford the IC power consumption. Therefore it is required to reduce the power consumption of individual transistors. A low-power transistor not only requires a low
operating voltage (Vdd), but also requires a low subthreshold swing (SS) to obtain a small off-
leakage current. In the conventional MOSFET, the subthreshold swing is limited to

60mV/dec by the Boltzman distribution of carriers. One of the switching mechanisms that can achieve a subthreshold swing less than 60mV/dec is the quantum mechanical tunneling between the conduction band and the valence band. Here, we analyze and optimize the tunneling field-effect transistor (TFET).

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Secondly, we simulated the device with varying the body doping concentration. As a result,

the leakage current increased as the body doping concentration was lowered (Figure 4.3). And the value of the leakage current was same as the body current (Figure 4.3). Therefore we can know that the leakage current at the off-state flows through the pn-junction between the body and the drain. Also, the pn-junction was reverse-biased and the reverse bias current at the pn-junction is inversely proportional to the doping concentration. For this reason, the leakage current increased when the body doping concentration increased.

참고 자료

C. Hu, D. Chou, P. Patel and A. Bowonder, “Green Transistor -A VDD Scaling Path for Future Low Power ICs,” Proc. Int. Symp. VLSI-TSA, pp. 14-15, Apr. 2008.

P. Patel, K. Jeon, A. Bowonder and C. Hu, “A Low Voltage Steep Turn-Off Tunnel Transistor Design,” Proc. Int. Conf. SISPAD, pp. 1-4, Sept. 2009.

A. Bowonder, P. Patel, K. Jeon, J. Oh, P. Majhi, H. Tseng and C. Hu, “Low-voltage green transistor using ultra shallow junction and hetero-tunneling,” Proc. Int. Workshop Junction Technology, pp. 93-96, May 2008.

A. Seabaugh and Q. Zhang, “Low-Voltage Tunnel Transistors for Beyond CMOS” Proc. IEEE, vol. 98, no. 12, pp. 2095&#8211;2110, Dec. 2010.

S. Argarwal, G. Klimeck and M. Luisier, “Leakage-Reduction Design Concepts for Low- Power Vertical Tunneling Field-Effect Transistors,” IEEE Electron Device Lett., vol. 31, no. 6, pp. 621-623, June 2010.