디지털공학실험 09. ROM,RAM 결과

목차

1. VHDL 코드
2. 결과 파형
3. 결론 및 고찰

본문내용

01. VHDL 코드
[ ROM VHDL Module Code ]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ROM is
Port ( Clock : in STD_LOGIC;
Read : in STD_LOGIC;
Address : in STD_LOGIC_VECTOR (1 downto 0);
Data_out : out STD_LOGIC_VECTOR (7 downto 0));
end ROM;

architecture Behavioral of ROM is
type ROM_Array is array (0 to 3) of std_logic_vector(7 downto 0);
constant Content: ROM_Array := (
0 => "10000001",
1 => "10000010",
2 => "10000011",
3 => "10000100",
OTHERS => "11111111");

begin
process(Clock)
begin
if( Clock'event and Clock = '0' ) then
if( Read = '1') then
Data_out <= Content(conv_integer(Address));
else
Data_out <= "ZZZZZZZZ";
end if;

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