디지털논리회로실험(Verilog HDL) - SR Latch, Level-Sensitive D-latch, D Flip-Flop
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- 2019.08.29
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소개글
디지털논리회로실험 레포트
목차
1. 관련이론
2. 실험
본문내용
2.실험
2.1 R-S latch
⓵ 실험목적 : Behavior 방식으로 SR Latch를 구현할 수 있다.
⓶ 실험내용
(1) Summary
We will show how to make use of these flip-flops in Part Ⅳ of this exercise. But first we will show how storage elements can be created in an FPGA without using its dedicated flip-flops. Figure 1 depicts a gated RS latch circuit.
(2) Process
⓵ Create a new project for the RS latch. Select as the target chip the Cyclone Ⅳ EP4CE115F29C7, which is the FPGA chip on the Altera DE2 board.
⓶ Generate a Verilog file with the code and include it in the project.
⓷ Compile the code. Use the Quartus RTL Viewer tool to examine the gate-level circuit produced from the code, and use the Technology Viewer tool to verify that the latch is implemented
⓸ Verify that the latch works as expected using both functional and timing simulation.
참고 자료
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