[공학]VHDL GATE MODEL링

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OR GATE 와 전가산기를 모델링

목차

Or gate data flow model
Or gate behavioral model
Or gate structural model
full adder code
Component을 사용한 16BIT FULL ADDER
Generate 문을 사용한 16BIT FULL ADDER

본문내용

library ieee;use ieee.std_logic_1164.all;entity OR1 is port ( I1, I2 : in bit ; O : out bit );end OR1 ;architecture OR_GATE of OR1 isbegin O <= I1 or I2;end OR_GATE;

library ieee;use ieee.std_logic_1164.all;entity OR2 is port ( I1, I2 : in bit ; O : out bit );end OR2 ;architecture OR_GATE of OR2 isbegin process(I1, I2) begin if(I1 = `0`) and (I2 = `0`) then O <= `0`; else O <= `1`; end if; end process;

library ieee;use ieee.std_logic_1164.all;entity COMPONENTS is port ( I1, I2 ,CIN : in bit ; S : out bit );end COMPONENTS ;architecture OR_GATE_COMPONENTS of COMPONENTS issignal O : bit ;component OR_GATEport( I1, I2 : in bit ; O : out bit);end component;begin u0: or_gate port map(I1 , I2 , O ); u1: or_gate port map(O , CIN , S

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