소개글
8 bit array multiplier 입니다.
verilog로 coding하였습니다.
컴파일 실행환경
ModelSim 등
본문내용
`timescale 1 ns / 10 ps
module array_mult8 (clk, rst, a, b, out);
input clk;
input rst;
input [7:0] a;
input [7:0] b;
output [15:0] out;
reg [15:0] out;
wire [15:0] out_t;
wire [7:0] t1;
wire [7:0] t2;
wire [7:0] t3;
wire [7:0] t4;
wire [7:0] t5;
wire [7:0] t6;
wire [7:0] t7;
wire [7:0] t8;
wire [6:0] s1;
wire [6:0] s2;
wire [6:0] s3;
wire [6:0] s4;
wire [6:0] s5;
wire [6:0] s6;
wire [6:0] s7;
wire [6:0] s8;
wire [6:0] c1;
wire [6:0] c2;
wire [6:0] c3;
wire [6:0] c4;
wire [6:0] c5;
wire [6:0] c6;
wire [6:0] c7;
wire [6:0] c8;
and U1 (t1[0], a[0], b[0]);
and U2 (t1[1], a[1], b[0]);
and U3 (t1[2], a[2], b[0]);
and U4 (t1[3], a[3], b[0]);
and U5 (t1[4], a[4], b[0]);
and U6 (t1[5], a[5], b[0]);
and U7 (t1[6], a[6], b[0]);
and U8 (t1[7], a[7], b[0]);
and U9 (t2[0], a[0], b[1]);
and U10 (t2[1], a[1], b[1]);
and U11 (t2[2], a[2], b[1]);
and U12 (t2[3], a[3], b[1]);
and U13 (t2[4], a[4], b[1]);
and U14 (t2[5], a[5], b[1]);
and U15 (t2[6], a[6], b[1]);
and U16 (t2[7], a[7], b[1]);
압축파일 내 파일목록
array_mult8.v
col_mult8.v
fa.v
fa_col.v
mux2.v
tb.v
tb_5.v
tb_6.v
tb_7.v
tb_8.v
참고 자료
없음