Full-adder를 이용한 16bit adder
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- 2008.12.07
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- 2007.12
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한컴오피스
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소개글
Full-adder를 이용한 16bit adder(구조적)
목차
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본문내용
library IEEE;
use IEEE.std_logic_1164.all;
entity adder16 is
port ( sum : buffer std_logic_vector(15 downto 0);
cout : out std_logic ;
A, B : in std_logic_vector (15 downto 0) ;
Cin : in std_logic );
end;
architecture structural of adder16 is
component Full_adder
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout : out std_logic);
end component;
signal carry : std_logic_vector(15 downto 0);
begin
cout <= carry(15);
A0 : Full_adder port map ( a(0), b(0), cin, sum(0), carry(0) ) ;
A1 : Full_adder port map ( a(1), b(1), carry(0), sum(1), carry(1) ) ;
A2 : Full_adder port map ( a(2), b(2), carry(1), sum(2), carry(2) ) ;
A3 : Full_adder port map ( a(3), b(3), carry(2), sum(3), carry(3) ) ;
A4 : Full_adder port map ( a(4), b(4), carry(3), sum(4), carry(4) ) ;
A5 : Full_adder port map ( a(5), b(5), carry(4), sum(5), carry(5) ) ;
참고 자료
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