소개글
4bit binary up/down counter PPT
(본 자료는 영어로 작성되었음)
목차
- Structural Description
State Diagram
State Table
Karnaugh Maps
Equations
Timing Diagram
- Behavioral Description
- Discussions
- References
(HDL ⇒ attachment)
본문내용
..FILE:HDL-Behavioral.v
//Behavioral description.
module updown_behavioral(Up,Down,CLK,A) ;
input Up,Down,CLK ;
output [3:0] A;
reg [3:0] A;
initial A = 0;
always @ (posedge CLK)
if (Up) A = A + 4`b0001;
else if (Down) A = A - 4`b0001;
else A = A;
endmodule
..FILE:HDL-Structural.v
//Structural description (Fig. 6-13)
module updown_str(Up,Down,CLK,A);
output [3:0] A;
input Up,Down,CLK;
wire[3:0] T,And_L,And_R,Or;
//Instantiate 4 AND/OR circuits:
AND_OR and_or0(Down,~Up,And_L[0],Up,Up,And_R[0],Or[0]),
and_or1(And_L[0],~A[0],And_L[1],And_R[0],A[0],And_R[1],Or[1]),
and_or2(And_L[1],~A[1],And_L[2],And_R[1],A[1],And_R[2],Or[2]),
and_or3(And_L[2],~A[2],And_L[3],And_R[2],A[2],And_R[3],Or[3]);
//Instaniate 4 T FFs:
T_FF to(Or[0],CLK,A[0]),
t1(Or[1],CLK,A[1]),
t2(Or[2],CLK,A[2]),
t3(Or[3],CLK,A[3]);
endmodule
//Description of AND/OR circuit.
module AND_OR(in1_L,in2_L,out_L,in1_R,in2_R,out_R,out_or);
output out_L, out_R, out_or;
이하생략
참고 자료
Alan B. Marcovitz. Introduction to Logic Design,2nd edition
M.Morris Mano. Digital Design, 3rd edition
Mano Kime. Logic and Computer Design Fundamentals, 3rd edition
Tokheim, Digital Electronics, 3rd edition
Morris E.Levine, Digital Theory and Experimentation Using Integrated Circuits
Barry Wilkinson, Digital System Design
Palnitkar,Samir, Verilog HDL
http://www.st.com/stonline/products/literature/ds/10323.pdf
http://www.doc.ic.ac.uk/~nd/surprise_96
http://homepages.ius.edu/JFDOYLE/c421/html/Ch11.htm
http://www.ibiblio.org/obp/books/socratic/output/ELTR145_sec2.pdf
http://www.interq.or.jp/japan/se-inoue/e_cpld5_1.htm