디지털 회로 실험 제 8장 입니다.

소개글

1. 실험 결과 보고서
2. 74LS76 JK Flip-Flop을 사용하여 4-bit 비동기형 up-down
counter를 설계하라.

목차

없음

본문내용

1. Construct a D latch by modifying the SR latch you built in the previous lab.
Connect D and CLK to two switches and Q and Q' to two logic monitors,
so you may verify its operation. Obtain a truth table of the circuit. Discuss the
differences between this latch and the SR latch.
2. Build a D flip-flop as shown below. Connect the D input to a switch and the
CLK to a pulser. Connect the outputs of the master latch to two logic monitors
and the outputs of the slave latch to another two logic monitors. Set the D
input to one and observe the outputs. Now set the D input to zero and
observe the outputs again. Discuss the transfer sequence from the input to
the master, then from the output of the master to the output of the slave,
Verify the flip-flop's operation and obtain a truth table for it.
3. Construct a master-slave JK flip-flop with two 74LS00 and one 74LS10.
Connect the J and K inputs to switches and the CLK input to a pulser. Repeat
the procedure described in the previous experiment to find the transfer sequence.
Discuss the differences between the D latch and the JK flip-flop, specially,
with regards to when the outputs of these devices are allowed to change.
2. 74LS76 JK Flip-Flop을 사용하여 4-bit 비동기형 up-down
counter를 설계하라.

참고 자료

없음