(vhdl소스)and or not latch mux 플립플롭 인코더

소개글

(vhdl소스)and or not latch mux F/F 인코더에 대한 vhdl소스와 테스트 벤치한 결과값입니다.

목차

-vhdl소스,테스트벤치 결과값-
and
or
not
latch
mux
F/F
인코더

본문내용

-AND Logic
1.VHDL코드
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and_ent is
Port ( input1 : in STD_LOGIC;
input2 : in STD_LOGIC;
output : out STD_LOGIC);
end and_ent;

architecture Behavioral of and_ent is
begin
process(input1,input2)
begin
if((input1=`1`)and(input2=`1`))then
output<=`1`;
else
output<=`0`;
end if;
end process;
end Behavioral;

2.Testbench코드
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_and_ent_vhd IS
END tb_and_ent_vhd;

ARCHITECTURE behavior OF tb_and_ent_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT and_ent
PORT(
input1 : IN std_logic;
input2 : IN std_logic;
output : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL input1 : std_logic := `0`;
SIGNAL input2 : std_logic := `0`;

--Outputs
SIGNAL output : std_logic;

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