비동기카운터 클럭

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비동기카운터 클럭,VHDL설계실험

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본문내용

CNT_4
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity cnt_4 is
port(
clk : in std_logic;
rst : in std_logic;
cnt_out : buffer std_logic_vector(3 downto 0);
clk_out : buffer std_logic
);
end cnt_4;

architecture behave of cnt_4 is
signal temp : std_logic_vector(2 downto 0):="000";
begin
process(clk, rst)
begin
if rst=`1` then
if clk`event and clk=`1` then
cnt_out<=cnt_out + 1;
end if;
else cnt_out<="0000";
end if;
end process;

process(clk, rst)
begin
if rst=`0` then
temp<="000";
clk_out<=`0`;
else
if clk`event and clk=`1` then
temp <= temp + 1;
if temp="100" then
temp<="000";
clk_out <= not clk_out;
end if;
end if;
end if;
end process;
end behave;

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